Abstract

Info

Title:: A low noise and low ripple front-end circuit for collecting scalp EEG signals

Author(s):: LI Hao; WANG Yuhan; XUE Kailong; YUAN Yi; LI Xiaolong; Department of Electronics and Information, Jiangsu University of Science and Technology, Zhenjiang 212003, China

Keywords:: Keywords: scalp EEG acquisition preamplifier chopping technology ripple rejection circuit programmable-gain amplifier

Abstract:: Abstract: Based on the SMIC 0.18 μm CMOS process, a front-end circuit for low noise scalp EEG acquisition, which composes preamplifier, ripple rejection circuit, programmable-gain amplifier (PGA) and low-pass filter, is proposed. The preamplifier employs the chopper technology to reduce the low-frequency noise and offset voltage. It is a capacitive-coupled chopper-stabilized amplifier, and its active amplification is a two-stage amplifier consisting of a differential folded-cascode stage and a differential common source stage in order to achieve a higher open-loop gain. At the output of the preamplifier, a parallel resistor-capacitor circuit is introduced to suppress the ripple at the chopping frequency. The PGA is a capacitive negative-feedback amplifier combined with an adjustable array, aiming to realize that the gain can be adjusted step by step. The results of Spectre post-simulation show that the preamplifier can achieve a voltage gain of 40 dB, a common mode rejection ratio (CMRR) of 131 dB, a power supply rejection ratio (PSRR) of 90 dB, and an equivalent input noise of 772 nV/sqrt (Hz) @ 100 Hz. The gain of the PGA can be set as 10 dB, 20 dB, 25 dB, respectively. The cut-off frequency of the low-pass filter is 1 kHz. The ripple at the chopping frequency can be suppressed 400-fold. As a result, the total gain of the front-end circuit is variable from 40 dB to 65 dB, and the passband is 1 Hz-1 kHz.